A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

Rexford D. Newbould; Jo Dale Carothers; Jeffrey J. Rodriguez; W. Timothy Holman

A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

Rexford D. Newbould
, Jo Dale Carothers
, Jeffrey J. Rodriguez
, W. Timothy Holman

Research output: Contribution to journal › Conference article › peer-review

Abstract

A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

Original language	English (US)
Pages (from-to)	IV/862-IV/865
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
State	Published - 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: May 26 2002 → May 29 2002

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{20a6bfa8e2ef4d9a9e663ce15ae7cd18,

title = "A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs",

abstract = "A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.",

author = "Newbould, \{Rexford D.\} and Carothers, \{Jo Dale\} and Rodriguez, \{Jeffrey J.\} and Holman, \{W. Timothy\}",

year = "2002",

language = "English (US)",

volume = "4",

pages = "IV/862--IV/865",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2002 IEEE International Symposium on Circuits and Systems ; Conference date: 26-05-2002 Through 29-05-2002",

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TY - JOUR

T1 - A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

AU - Newbould, Rexford D.

AU - Carothers, Jo Dale

AU - Rodriguez, Jeffrey J.

AU - Holman, W. Timothy

PY - 2002

Y1 - 2002

N2 - A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

AB - A method is presented for embedding the same watermark multiple times into a single integrated circuit design using a hierarchy of incorporation techniques. This has the advantage of adding multiple independent signatures to the circuit in order to better resist large-scale attacks. A high degree of robustness is provided by requiring attacks on multiple stages of the VLSI design flow in order to properly efface the mark.

UR - https://www.scopus.com/pages/publications/0036290965

UR - https://www.scopus.com/pages/publications/0036290965#tab=citedBy

M3 - Conference article

AN - SCOPUS:0036290965

SN - 0271-4310

VL - 4

SP - IV/862-IV/865

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2002 IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

Abstract

ASJC Scopus subject areas

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