A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs

Alexander Fusco; Sahil Hassan; Joshua Mack; Ali Akoglu

doi:10.1109/VLSI-SoC54400.2022.9939623

A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs

Alexander Fusco, Sahil Hassan, Joshua Mack, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of PEs creates the necessity of deploying a scheduler as an overlay processor in hardware to be able to make scheduling decisions rapidly and enable deployment of real-life applications on heterogeneous SoCs. In this study we present the design trade-offs involved for implementing and deploying the runtime variant of the heterogeneous earliest finish time algorithm (HEFTRT) on the FPGA. We conduct performance evaluations on an SoC configuration emulated over the Xilinx Zynq ZCU102 platform. In a runtime environment we demonstrate hardware-based HEFTRT's ability to make scheduling decisions with 9.144 ns latency on average, process 26.7% more tasks per second compared to its software counterpart, and reduce the scheduling latency by up to a factor of 183 based on workloads composed of a mixture of dynamically ×arriving real-life signal processing applications.

Original language	English (US)
Title of host publication	Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022
Publisher	IEEE Computer Society
ISBN (Electronic)	9781665490054
DOIs	https://doi.org/10.1109/VLSI-SoC54400.2022.9939623
State	Published - 2022
Event	30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022 - Patras, Greece Duration: Oct 3 2022 → Oct 5 2022

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume	2022-October
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022
Country/Territory	Greece
City	Patras
Period	10/3/22 → 10/5/22

Keywords

FPGA
Scheduling
hardware emulation
multiprocessor SoC
system on chip

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC54400.2022.9939623

Cite this

Fusco, A., Hassan, S., Mack, J., & Akoglu, A. (2022). A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs. In Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2022-October). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC54400.2022.9939623

A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs. / Fusco, Alexander; Hassan, Sahil; Mack, Joshua et al.
Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022. IEEE Computer Society, 2022. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2022-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fusco, A, Hassan, S, Mack, J & Akoglu, A 2022, A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs. in Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, vol. 2022-October, IEEE Computer Society, 30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, 10/3/22. https://doi.org/10.1109/VLSI-SoC54400.2022.9939623

Fusco A, Hassan S, Mack J, Akoglu A. A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs. In Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022. IEEE Computer Society. 2022. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC54400.2022.9939623

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abstract = "Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of PEs creates the necessity of deploying a scheduler as an overlay processor in hardware to be able to make scheduling decisions rapidly and enable deployment of real-life applications on heterogeneous SoCs. In this study we present the design trade-offs involved for implementing and deploying the runtime variant of the heterogeneous earliest finish time algorithm (HEFTRT) on the FPGA. We conduct performance evaluations on an SoC configuration emulated over the Xilinx Zynq ZCU102 platform. In a runtime environment we demonstrate hardware-based HEFTRT's ability to make scheduling decisions with 9.144 ns latency on average, process 26.7% more tasks per second compared to its software counterpart, and reduce the scheduling latency by up to a factor of 183 based on workloads composed of a mixture of dynamically ×arriving real-life signal processing applications.",

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AB - Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based scheduler with the increased heterogeneity level in terms of number and types of PEs creates the necessity of deploying a scheduler as an overlay processor in hardware to be able to make scheduling decisions rapidly and enable deployment of real-life applications on heterogeneous SoCs. In this study we present the design trade-offs involved for implementing and deploying the runtime variant of the heterogeneous earliest finish time algorithm (HEFTRT) on the FPGA. We conduct performance evaluations on an SoC configuration emulated over the Xilinx Zynq ZCU102 platform. In a runtime environment we demonstrate hardware-based HEFTRT's ability to make scheduling decisions with 9.144 ns latency on average, process 26.7% more tasks per second compared to its software counterpart, and reduce the scheduling latency by up to a factor of 183 based on workloads composed of a mixture of dynamically ×arriving real-life signal processing applications.

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A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this