Abstract
This paper presents an efficient methodology for automatic routing of analog circuits. The analog routing techniques presented here, when combined with our previous and ongoing work in digital routing, will provide an integrated mixed-signal routing environment. Routing in analog VLSI is much more complex than that in digital VLSI circuits. Unlike digital VLSI routing, the goal in analog routing is not simply to minimize area or reduce total interconnect length. Performance constraints such as matching of parasitics on differential pairs, effects of parasitic capacitance on signal nets, and voltage drops, especially in high current nets, need to be considered and satisfied. The algorithm described in this work generates candidate routes for all nets to be considered simultaneously for compatibility and allows for incorporation of flexible models for addressing the analog-specific concerns.
Original language | English (US) |
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Pages (from-to) | 442-446 |
Number of pages | 5 |
Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
State | Published - 2001 |
Event | 14th Annual IEEE International ASIC/SOC Conference- System-on-Chip in a Networked World- - Arlington, VA, United States Duration: Sep 12 2001 → Sep 15 2001 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering