TY - JOUR
T1 - A Fast on-Chip Profiler Memory Using a Pipelined Binary Tree
AU - Lysecky, Roman
AU - Cotterell, Susan
AU - Vahid, Frank
N1 - Funding Information:
Manuscript received August 21, 2002; revised February 10, 2003. This work was supported in part by the National Science Foundation (CCR-9876006), in part by the the UC MICRO program, and in part by a Department of Education GAANN Fellowship.
PY - 2004/1
Y1 - 2004/1
N2 - We introduce a novel memory architecture that can count the occurrences of patterns on a system's bus, a task known as profiling. Such profiling can serve a variety of purposes, like detecting a microprocessor's software hot spots or frequently used data values, which can be used to optimize various aspects of the system. The memory, which we call ProMem, is based on a pipelined binary search tree structure, yielding several beneficial features, including nonintrusiveness, accurate counts, excellent size and power efficiency, very fast access times, and the use of standard memories with only simple additional logic. The main limitation is that the set of potential patterns must be preloaded into the memory. We describe the ProMem architecture, and show excellent size and performance advantages compared with content-addressable memory (CAM) based designs.
AB - We introduce a novel memory architecture that can count the occurrences of patterns on a system's bus, a task known as profiling. Such profiling can serve a variety of purposes, like detecting a microprocessor's software hot spots or frequently used data values, which can be used to optimize various aspects of the system. The memory, which we call ProMem, is based on a pipelined binary search tree structure, yielding several beneficial features, including nonintrusiveness, accurate counts, excellent size and power efficiency, very fast access times, and the use of standard memories with only simple additional logic. The main limitation is that the set of potential patterns must be preloaded into the memory. We describe the ProMem architecture, and show excellent size and performance advantages compared with content-addressable memory (CAM) based designs.
KW - Binary search tree
KW - Design
KW - High performance
KW - Memory
KW - On-chip profiler
KW - Pipelined binary search tree
KW - Profiling
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U2 - 10.1109/TVLSI.2003.820522
DO - 10.1109/TVLSI.2003.820522
M3 - Article
AN - SCOPUS:1342286835
SN - 1063-8210
VL - 12
SP - 120
EP - 122
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
ER -