A fast on-chip profiler memory

Roman Lysecky, Susan Cotterell, Frank Vahid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations


Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profiling techniques suffer from runtime overhead, inaccuracy, or slowness, and the traditional non-intrusive method of using a logic analyzer doesn't work for today's system-on-a-chip having embedded cores. We introduce a novel on-chip memory architecture that overcomes these limitations. The architecture, which we call ProMem, is based on a pipelined binary tree structure. It achieves single-cycle throughput, so it can keep up with today's fastest pipelined processors. It can also be laid out efficiently and scales very well, becoming more efficient the larger it gets. The memory can be used in a wide-variety of common profiling situations, such as instruction profiling, value profiling, and network traffic profiling, which in turn can be used to guide numerous design automation tasks.

Original languageEnglish (US)
Title of host publicationProceedings of the 39th Annual Design Automation Conference, DAC'02
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)1581134614
StatePublished - 2002
Event39th Design Automation Conference - New Orleans, LA, United States
Duration: Jun 10 2002Jun 14 2002

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference39th Design Automation Conference
Country/TerritoryUnited States
CityNew Orleans, LA


  • Adaptive architectures
  • Binary tree
  • Embedded CAD
  • Embedded systems
  • Low power
  • Memory design
  • Platform tuning
  • Profiling
  • System-on-a-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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