A configurable logic architecture for dynamic hardware/software partitioning

Roman Lysecky, Frank Vahid

Research output: Chapter in Book/Report/Conference proceedingConference contribution

54 Scopus citations


In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specifically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory, and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04
EditorsG. Gielen, J. Figueras
Number of pages6
StatePublished - 2004
EventProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04 - Paris, France
Duration: Feb 16 2004Feb 20 2004

Publication series

NameProceedings - Design, Automation and Test in Europe Conference and Exhibition


OtherProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04


  • Codesign
  • Configurable logic
  • Dynamic optimization
  • FPGA fabric
  • Hardware/software partitioning
  • Just-in-time compilation
  • Place and route
  • Platforms
  • Reconfigurable computing
  • Self-improving chips
  • Synthesis
  • System-on-a-chip
  • Warp processors

ASJC Scopus subject areas

  • Engineering(all)


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