TY - GEN
T1 - A clustering based area I/O planning for flip-chip technology
AU - Wang, Janet
AU - Muchherla, Kishore Kumar
AU - Kumar, Jai Ganesh
PY - 2004
Y1 - 2004
N2 - The complexity of nanometer SoC design requires the co-design and development of circuit design and packaging technology to enable a successful 'total integrated solution'. In this paper we introduce a new area I/O algorithm for the recent flip-chip packaging technology. The algorithm combines a clustering technique with area I/O planning algorithm to avoid iterations during "placement and area I/O pad assignment". Experiment results show that the total interconnect length (including both on-chip and off-chip parts) and delay are reduced by 10-15% comparing with traditional algorithms.
AB - The complexity of nanometer SoC design requires the co-design and development of circuit design and packaging technology to enable a successful 'total integrated solution'. In this paper we introduce a new area I/O algorithm for the recent flip-chip packaging technology. The algorithm combines a clustering technique with area I/O planning algorithm to avoid iterations during "placement and area I/O pad assignment". Experiment results show that the total interconnect length (including both on-chip and off-chip parts) and delay are reduced by 10-15% comparing with traditional algorithms.
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U2 - 10.1109/ISQED.2004.1283673
DO - 10.1109/ISQED.2004.1283673
M3 - Conference contribution
AN - SCOPUS:2942683259
SN - 0769520936
SN - 9780769520933
T3 - Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
SP - 196
EP - 201
BT - Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
PB - IEEE Computer Society
T2 - Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
Y2 - 22 March 2004 through 24 March 2004
ER -