@inproceedings{33c2fd29a998447eb5db1d04cd3a64a7,
title = "A 320MHz-2.56GHz low jitter phase-locked loop with adaptive-bandwidth technique",
abstract = "This paper presents a novel adaptive-bandwidth phase-locked loop (PLL) using a closed loop voltage controlled oscillator (VCO). The adaptive-bandwidth PLL uses the gain of closed loop VCO to obtain a constant unity gain bandwidth over an operating frequency range. Furthermore, a charge pump (CP) current is proportional to the current of VCO so that CP current is in proportion to the VCO frequency. Since the adaptive-bandwidth is optimized over the VCO frequency, an integrated RMS jitter is reduced in comparison to a conventional fixed-bandwidth PLL. We simulate the proposed PLL in 130 nm CMOS technology at 1.2 V power supply. The integrated RMS jitter of the proposed adaptive-bandwidth PLL is 2.35 psec which is 70% smaller than the conventional PLL. This adaptive-bandwidth PLL consumes 2.6 mW at 2.56 GHz output frequency.",
keywords = "adaptive-bandwidth, closed loop voltage controlled oscillator (VCO), jitter, phase-locked loop (PLL)",
author = "Jung, {Seok Min} and Roveda, {Janet Meiling}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 28th IEEE International System on Chip Conference, SOCC 2015 ; Conference date: 08-09-2015 Through 11-09-2015",
year = "2016",
month = feb,
day = "12",
doi = "10.1109/SOCC.2015.7406906",
language = "English (US)",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "40--43",
editor = "Thomas Buchner and Danella Zhao and Karan Bhatia and Ramalingam Sridhar",
booktitle = "Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015",
}