TY - GEN
T1 - 4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs
AU - Canan, Talha Furkan
AU - Kaya, Savas
AU - Karanth, Avinash
AU - Louri, Ahmed
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/23
Y1 - 2020/11/23
N2 - We report on four-input NAND and NOR gates using only two 7nm Schottky-Barrier (SB) independent-gate FinFETs transistors that take advantage of gate workfunction engineering (WFE). Careful optimization of workfunctions at the source/drain contacts as well as two independent gates of the SB-FinFETs provide unprecedented control of the threshold in the ambipolar device operation. It is used in this work to tailor 4-input NAND and NOR functionalities out of only two transistors (2T), utilizing only two different metal workfunctions in a given gate. Correct operation of multi-input gates for supply voltages as low as VDD = 0.5V has been verified using 2D TCAD circuit simulations. Switching performance of the proposed 4-input gates indicate that they have 45% reduction in power-delay product (PDP) as compared to the conventional 16T FinFET counterparts, which is due to substantially lower power dissipation at the expense of slower transitions. A JK Flip-Flop circuit is designed using the proposed four-input NAND gate that illustrates its advantages for the logic operation.
AB - We report on four-input NAND and NOR gates using only two 7nm Schottky-Barrier (SB) independent-gate FinFETs transistors that take advantage of gate workfunction engineering (WFE). Careful optimization of workfunctions at the source/drain contacts as well as two independent gates of the SB-FinFETs provide unprecedented control of the threshold in the ambipolar device operation. It is used in this work to tailor 4-input NAND and NOR functionalities out of only two transistors (2T), utilizing only two different metal workfunctions in a given gate. Correct operation of multi-input gates for supply voltages as low as VDD = 0.5V has been verified using 2D TCAD circuit simulations. Switching performance of the proposed 4-input gates indicate that they have 45% reduction in power-delay product (PDP) as compared to the conventional 16T FinFET counterparts, which is due to substantially lower power dissipation at the expense of slower transitions. A JK Flip-Flop circuit is designed using the proposed four-input NAND gate that illustrates its advantages for the logic operation.
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U2 - 10.1109/ICECS49266.2020.9294892
DO - 10.1109/ICECS49266.2020.9294892
M3 - Conference contribution
AN - SCOPUS:85099482061
T3 - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
BT - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020
Y2 - 23 November 2020 through 25 November 2020
ER -