TY - GEN
T1 - 3D-NoC
T2 - 2012 IEEE 30th International Conference on Computer Design, ICCD 2012
AU - Morris, Randy
AU - Kodi, Avinash Karanth
AU - Louri, Ahmed
PY - 2012
Y1 - 2012
N2 - The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.
AB - The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.
UR - http://www.scopus.com/inward/record.url?scp=84872092518&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84872092518&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2012.6378672
DO - 10.1109/ICCD.2012.6378672
M3 - Conference contribution
AN - SCOPUS:84872092518
SN - 9781467330503
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 413
EP - 418
BT - 2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Y2 - 30 September 2012 through 3 October 2012
ER -