3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores

Randy Morris, Avinash Karanth Kodi, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations


The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.

Original languageEnglish (US)
Title of host publication2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Number of pages6
StatePublished - 2012
Event2012 IEEE 30th International Conference on Computer Design, ICCD 2012 - Montreal, QC, Canada
Duration: Sep 30 2012Oct 3 2012

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404


Other2012 IEEE 30th International Conference on Computer Design, ICCD 2012
CityMontreal, QC

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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