TY - GEN
T1 - 100 Gbit/s authenticated encryption based on quantum key distribution
AU - Muehlberghuber, Michael
AU - Keller, Christoph
AU - Felber, Norbert
AU - Pendl, Christian
PY - 2012
Y1 - 2012
N2 - We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 133 Gbit/s on an Altera Stratix IV FPGA. The design requires 30 kALMs and runs at a maximum clock frequency of 260 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date.
AB - We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 133 Gbit/s on an Altera Stratix IV FPGA. The design requires 30 kALMs and runs at a maximum clock frequency of 260 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date.
KW - AES
KW - Authenticated encryption
KW - FPGA
KW - GCM
KW - High-throughput architecture
KW - OCB
KW - Pipelining
KW - Serpent
UR - http://www.scopus.com/inward/record.url?scp=84872188562&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84872188562&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2012.6379017
DO - 10.1109/VLSI-SoC.2012.6379017
M3 - Conference contribution
AN - SCOPUS:84872188562
SN - 9781467326568
T3 - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Proceedings
SP - 123
EP - 128
BT - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Proceedings
T2 - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012
Y2 - 7 October 2012 through 10 October 2012
ER -