100 Gbit/s authenticated encryption based on quantum key distribution

Michael Muehlberghuber; Christoph Keller; Norbert Felber; Christian Pendl

doi:10.1109/VLSI-SoC.2012.7332088

100 Gbit/s authenticated encryption based on quantum key distribution

Michael Muehlberghuber, Christoph Keller, Norbert Felber, Christian Pendl

Mathematics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 133 Gbit/s on an Altera Stratix IV FPGA. The design requires 30 kALMs and runs at a maximum clock frequency of 260 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date.

Original language	English (US)
Title of host publication	2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012
Publisher	IEEE Computer Society
Pages	123-128
Number of pages	6
ISBN (Electronic)	9781467326582
DOIs	https://doi.org/10.1109/VLSI-SoC.2012.7332088
State	Published - Nov 18 2015
Event	IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012 - Santa Cruz, United States Duration: Oct 7 2012 → Oct 10 2012

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume	07-10-October-2012
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012
Country/Territory	United States
City	Santa Cruz
Period	10/7/12 → 10/10/12

Keywords

AES
Authenticated encryption
FPGA
GCM
High-throughput architecture
OCB
Pipelining
Serpent

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2012.7332088

Cite this

Muehlberghuber, M., Keller, C., Felber, N., & Pendl, C. (2015). 100 Gbit/s authenticated encryption based on quantum key distribution. In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012 (pp. 123-128). [7332088] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 07-10-October-2012). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2012.7332088

100 Gbit/s authenticated encryption based on quantum key distribution. / Muehlberghuber, Michael; Keller, Christoph; Felber, Norbert et al.

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012. IEEE Computer Society, 2015. p. 123-128 7332088 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 07-10-October-2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Muehlberghuber, M, Keller, C, Felber, N & Pendl, C 2015, 100 Gbit/s authenticated encryption based on quantum key distribution. in 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012., 7332088, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, vol. 07-10-October-2012, IEEE Computer Society, pp. 123-128, IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, United States, 10/7/12. https://doi.org/10.1109/VLSI-SoC.2012.7332088

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abstract = "We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 133 Gbit/s on an Altera Stratix IV FPGA. The design requires 30 kALMs and runs at a maximum clock frequency of 260 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date.",

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100 Gbit/s authenticated encryption based on quantum key distribution

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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