Engineering
Interconnects
100%
Process Variation
77%
Experimental Result
73%
Crosstalk
41%
Nanometre
27%
Circuit Performance
26%
Feature Size
25%
Circuit Design
24%
Driver Model
20%
Circuit Model
17%
Simulators
17%
Negative Differential Resistance
17%
Induced Noise
17%
Fixed Points
17%
Discrete Model
17%
Health Monitoring
17%
Power Supply
17%
Transients
15%
Analyse Variability
13%
Statistical Variation
13%
Process Variability
13%
Input Multiple
13%
Body Sensor Network
13%
Control Cycle
13%
Resonant Tunneling
13%
Point Method
13%
Network-on-Chip
13%
Linear Circuit
13%
Passivity
13%
Circuit Simulation
12%
Transformation Matrix
11%
Supply Voltage
11%
Parametric Uncertainty
11%
Circuit Parameter
10%
Smart Grid
10%
Integrated Circuit Design
10%
Electric Power Utilization
10%
Phase Locked Loop
10%
Current-Voltage Characteristic
10%
Slew Rate
10%
System-on-Chip
10%
Subspace Method
10%
Electric Lines
10%
Nodes
10%
Component Analysis
9%
Parameter Variation
9%
Simulation Result
9%
Metrics
9%
Negative-Bias Temperature Instability
9%
Output Frequency
9%
Keyphrases
Process Variation
38%
Parameter Reduction
27%
Analog Mixed-Signal
20%
Mixed-signal Design
20%
Switching Window
20%
Linear Fractional Transform
20%
Crosstalk Noise
17%
Circuit Performance
17%
Balanced Truncation
15%
Driver Model
13%
Hessian
13%
Variability Analysis
13%
RLC Interconnects
13%
Uncertainty Reduction
13%
Delay Uncertainty
13%
Multiple Input Switching
13%
Directional Dependence
13%
Non-iterative Model
13%
Distributed Interconnect
13%
Interconnected Networks
13%
Reduction Method
11%
Process Variability
11%
Gate Delay
11%
Delay Variation
11%
Model Order Reduction
10%
Continuous Switching
10%
Parametric Uncertainty
10%
Heart Rate Variability
9%
Circuit Model
9%
Robust Design
9%
Robust Optimization Problem
9%
Negative Differential Resistance
9%
Model Uncertainty
9%
Interconnect Delay
9%
Multiple Solutions
9%
Induced Delay
9%
Fixed-point Iteration
8%
Linear Matrix Inequality
8%
Increasing Process
8%
Performance Variability
7%
Uncertain Structures
7%
Lur'e Equations
7%
Nanometer Technology
7%
Recovery-oriented Services
6%
Loop Voltage
6%
Parametric Yield
6%
Design-manufacturing Interface
6%
Finite Point Method
6%
Time Synchronization Algorithm
6%
Fractional Approach
6%
Computer Science
Experimental Result
34%
Process Variation
27%
Circuit Simulation
20%
Simulation Approach
20%
Fixed Points
20%
Point Iteration
20%
Delay Variation
20%
linear matrix
20%
Interconnect Parameter
17%
Side Channel Attack
13%
Smart Grid
13%
Clock Skew
13%
Simulation Mode
13%
Matching Model
13%
Side Channel
11%
Routing Algorithm
10%
Parameter Variation
10%
Mobile Platform
9%
Principle Component Analysis
8%
Hardware Component
6%
Underlying Hardware
6%
Case Study
6%
Monitoring Application
6%
Mitosis Detection
6%
Probabilistic Analysis
6%
Matching Algorithm
6%
Processor Cache
6%
User Behavior
6%
Star Topology
6%
Concurrency
6%
Analog Circuit
6%
Segmentation Approach
6%
And Gate
6%
Timing Analysis
6%
Performance Variation
6%
Data Fusion
6%
Distributed Systems
6%
Chip Technology
6%
Combinational Circuit
6%
Multicore System
6%
Workload Balancing
6%
Traditional Workload
6%
Supply Voltage
6%
Communication Capacity
6%
Modern Medicine
6%
Transmission Line
6%
Baseline Wander
6%
Internal Source
6%
Norton Equivalent
6%
Equivalent Circuit
6%
